View HY5W2A6CSF-HF_7182271.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t-f hy5w26cf-f / hy57w281620hct-f 4banks x 2m x 16bits synchronous dram this document is a general product descripti on and is subject to change without notice. hynix does not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 1.3 / dec. 01 description the hynix low power sdram is suited for non-pc ap plication which use the ba tteries such as pdas, 2.5g and 3g cellular phones with internet access and multimedia c apabilities, mini-n otebook, handheld pcs. the hynix hy5w2a6cf is a 134,217,728bit cmos synchronous dynamic random access memory. it is organized as 4banks of 2,097,152x16. the low power sdram provides for programmable options including cas latency of 1, 2, or 3, read or write burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). and the low power sdram also provides for special programmable options incl uding partial array self refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, temperature compensated self refresh of 15, 45, 70, or 85 degrees c. a burst of read or write cycles in pr ogress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write com- mand on any cycle(this pipelined desi gn is not restricted by a 2n rule). deep power down mode is a addit ional operating mode for low power sdram. this mode can achieve maximum power reduction by removing power to t he memory array within each sdram. by using this feature, the system can cut off alomost all dram powe r without adding the cost of a power switch and giving up mother-b oard power-line layout flexibility. features ? standard sdram protocol ? internal 4bank operation ? voltage : vdd = 2.5v, vddq = 1.8v & 2.5 v ? lvttl compatible i/o interface ? low voltage interface to reduce i/o power ? low power features ( hy5w26cf / hy57w281620hct series can?t support these features) - pasr(partial array self refresh) - tcsr(temperature comp ensated self refresh) - deep power down mode ? cas latency of 1, 2, or 3 ? packages : 54ball, 0.8mm pitch fbga / 54pin, tsop ? -25 ~ 70c operation 128m sdram oderin g information part number clock frequency cas latency organization interface package hy5w2a6c(l/s)f-hf hy5w26cf-hf hy57w2a1620hc(l/s)t-hf hy57w281620hct-hf 133mhz 3 4banks x 2mb x 16 lvttl 54ball fbga (hy5xxxxxxf) 54pin tsop-ii (hy5xxxxxxt) hy5w2a6c(l/s)f-pf hy5w26cf-pf hy57w2a1620hc(l/s)t-pf hy57w281620hct-pf 100mhz 2 4banks x 2mb x 16 lvttl hy5w2a6c(l/s)f-sf hy5w26cf-sf hy57w2a1620hc(l/s)t-sf hy57w281620hct-sf 100mhz 3 4banks x 2mb x 16 lvttl hhy5w2a6c(l/s)f-bf hy5w26cf-bf hy57w2a1620hc(l/s)t-bf hy57w281620hct-bf 66mhz 2 4banks x 2mb x 16 lvttl * hy5xxxxxx-b series can suppor t 40mhz cl1 and 33mhz cl1.
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 3 ball configuration a b c d e f g h j 54 ball fbga 0.8 mm b a l l p i t c h vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 clk vss udqm a11 cke nc a9 a8 a7 a6 vss a5 a4 nc 1 2 3 a b c d e f g h j vddq vddq vssq vssq vdd dq0 vdd vdd dq2 dq1 dq4 dq3 dq6 dq5 dq7 ldqm /cas /ras /we a3 a2 a0 a1 a10 /cs ba0 ba1 7 8 9 9 8 7 3 2 1 < top view > < bottom view >
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 4 ball description note. please find hy5xxxxxxt series for standard 54tsop-ii pin configuration & description. ball out symbol type description f2 clk input clock : the system clock input. all other inputs are registered to the sdram on the rising edge of clk f3 cke input clock enable : controls inte rnal clock signal and when deacti- vated, the sdram will be one of the states among power down, suspend or self refresh g9 cs input chip select : enables or disabl es all inputs e xcept clk, cke, udqm and ldqm g7,g8 ba0, ba1 input bank addr ess : selects bank to be activated during ras activ- ity selects bank to be read/written during cas activity h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0 ~ a11 input row address : ra0 ~ ra11, column address : ca0 ~ ca8 auto-precharge flag : a10 f8, f7, f9 ras , cas , we input command inputs : ras , cas and we define the operation refer function trut h table for details f1, e8 udqm, ldqm input data mask:controls output buffers in read mode and masks input data in write mode a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0 ~ dq15 i/o data input/output:multiplex ed data input/output pin a9, e7, j9, a1, e3, j1 vdd/vss supply power supply for internal circuits a7, b3, c7, d3, a3, b7, c3, d7 vddq/ vssq supply power supply for output buffers e2, g1 nc - no connection
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 5 functional block diagram 2mbit x 4banks x 16 i/o low power synchronous dram state machine row pre decoders column pre decoders extended mode register self refresh logic & timer tcsr, pasr internal row counter row decoders 2mx16 bank3 2mx16 bank2 2mx16 bank1 2mx16 bank0 row decoders row decoders row decoders column decoders memory cell array refresh column active clk cke cs ras cas we u/ldqm address registers column add counter mode register address buffers data out control burst counter sense amp & i/o gate i/o buffer & logic a0 a1 dq0 dq15 a11 ba1 ba0 row active bank select cas latency burst length
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 6 basic functional description mode register cas latency burst type burst leng th ba1 ba0 a12a11a10a9a8a7a6a5a4a3a2a1a0 0 0 0 0 0 0 0 0 cas latency bt burst length a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved a3 burst type 0 sequential 1 interleave a2 a1 a0 burst length a3 = 0 a3=1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 7 basic functional description (continued) extended mode register tcsr (temperature compensated self refresh) pasr (partial array self refresh) ba1 ba0 a12 a11 a10a9a8a7a6a5a4a3a2a1 a0 1 0 0 0 0 0 0 0 0 0 tcsr pasr a4 a3 temperature o c 0 0 70 0 1 45 1 0 15 1 1 85 a2 a1 a0 self refresh coverage 0 0 0 all banks 0 0 1 half of total bank (ba1=0) 0 1 0 quarter of total bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved 1 0 1 one eighth of total bank (row address msb=0) 1 1 0 one sixteenth of total bank (row address 2 msbs=0) 1 1 1 reserved
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 8 power up and initialization like a synchronous dram, low power sdram must be powered up and initialized in a predefined manner. power must be applied to vdd and vddq(simultaneously). the clock signal must be started at th e same time. after power up, an initial pause of 200 sec is required. and a precharge all co mmand will be issued to the lp sdra m. then, 8 or more auto refresh cycles will be provided. after the auto refres h cycles are completed, a mode register set(mrs) command will be issued to program the specific mode of operation (cas latency, burs t length, etc.) and a extended mode register set command will be issued to program specific mode of self refresh operat ion(pasr & tcsr). th e following these cycles, the lp sdram is ready for normal opeartion. programming the registers mode register the mode register contains the specific mo de of operation of the lp sdram. this register includes the selection of a burst length(1, 2, 4, 8, full page), a cas latency(1, 2, or 3), a burst type, an opearting mode to differentiate between normal mode and a special burst read and single write mode. the mode register set must be done before any activate command after the power up sequence. any contents of the mode register be al tered by re-programming the mode register through the execu- tion of mode register set command. extended mode register the extended mode register contains the s pecific features of self re fresh opeartion of the lp sdram. this register includes the selection of partial arrays to be refreshed(half array, quar ter array, etc.), tempearture range of the device(85, 70, 45, 15) for reducing current consumption during self refresh. th e extended mode register set must be done before any activate command after the power up sequence. any contents of the mode register be altered by re-p rogramming the mode register through the execution of extended mode register set command. bank(row) active the bank active command is used to activate a row in a specifie d bank of the device. this command is initiated by activating cs , ras and deasserting cas , we at the positive edge of the clock. the va lue on the ba1 and ba0 selects the bank, and the value on the a0-a11 selects the row. this row remains active for column access until a precharge command is issued to that bank. read and write opeartions can only be initiated on this activated ban k after the minimum trcd time is passed from the activate command. read the read command is used to initiate the burst read of data. this command is initiated by activating cs , cas , and deas- serting we , ras at the positive edge of the clock. ba1 and ba0 in puts select the bank, a8-a0 address inputs select the sarting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain active for subseq uent accesses.the length of burst and the cas latency will be determined by the values pro- grammed during the mrs command. write the write command is used to initia te the burst write of data. this co mmand is initiated by activating cs , cas , we and deasserting ras at the positive edge of the clock. ba1 and ba0 inpu ts select the bank, a8-a0 address inputs select the starting column location. the value on input a10 determines wh ether or not auto precharge is used. if auto precharge is selected the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain active for subsequent accesses.
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 9 precharge the precharge command is used to close the open row in a particular bank or the open row in all banks. when the precharge command is issued with address a1 0, high, then all banks will be precharged, and if a10 is lo w, the open row in a particular bank will be precharged. the bank(s) will be available when the minimum trp time is met after the precha rge command is issued. auto precharge the auto precharge command is issued to close the open row in a particular bank after read or write operation. if a10 is high when a read or write command is issued, t he read or write with auto precharge is initiated. burst termination the burst termination is used to termi nate the burst operation. this function can be accomplished by asserting a burst stop command or a precharge command during a burst read or write operation. the precharge command interrupts a burst cycle and close the active bank, and the burst stop command terminates the existing burst operation leave the bank open. data mask the data mask comamnd is used to mask read or write data . during a read operation, when this command is issued, data ouputs are disabled and become high impedance after tw o clock delay. during a write operation, when this command is issued, data inputs can?t be written with no clock delay. clock suspend the clock suspend command is used to suspend the internal clock of dram. during normal access mode, cke is keeping high. when cke is low, it freeze s the internal clock and extends data read and write operations. power down the power down command is used to reduce standby current. be fore this command is issued, all banks must be precharged and trp must be passed after a precharge command. once t he power down command is initia ted by keeping cke low, all of the input buffer exc ept cke are gated off. auto refresh the auto refresh command is used during normal operation and is similar to cbr refresh in coventional drams. this com- mand must be issued each time a refresh is required. when an auto refresh command is issued , the address bits is ?don?t care?, because the specific address bits is ge nerated by internal refresh address counter. self refresh the self refresh command is used to re tain cell data in the low power sdram. in the self refresh mode, the low power sdram operates refresh cycle asynchronously. the self refr esh command is initiated like an auto refresh command ex- cept cke is disabled(low). the low power sdram can acco mplish an special self refres h operation by the specific modes(tcsr, pasr) programmed in extended mode registers. the low power sdram can control the refresh rate by the temperature value of tcsr (temperature compensated self refresh) and select the memory array to be refreshed by the value of pasr(partial array self refres h). the low power sdram can reduce the self refresh cu rrent(idd6) by using these two modes. deep power down the deep power down mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. for more information, see the special operation for low power consumption of this data sheet.
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 10 command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high. 2. ba1/ba0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set. function cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code 2 extended mode register set h x l l l l x op code 2 no operation h x l h h h x x device deselect h x h x x x x x bank active h x l l h h x row address v read h x l h l h column l v read with autoprecharge h x l h l h x column h v write h x l h l l x column l v write with autoprecharge h x l h l l x column h v precharge all banks h x l l h l x x h x precharge selected bank h x l l h l x x l v burst stop h x l h h l x x data write/output enable h x x x x data mask/output disable h x x v x auto refresh h h l l l h x x self refresh entry h l l l l h x x self refresh exit l h h x x x x x 1 l h h h precharge power down entry h l h x x x x x l h h h precharge power down exit l h h x x x x x l h h h clock suspend entry h l h x x x x x l v v v clock suspend exit l h x x x deep power down entry h l l h h l x x deep power down exit l h x x x
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 11 current state truth table (sheet 1 of 3) current state command action notes cs ras cas we ba0,ba1 a11-a0 description idle l l l l op code mode register set set the mode register 14 l l l h x x auto or self refresh start auto or self refresh 5 l l h l ba x precharge no operation l l h h ba row add. bank activate activate the specified bank and row l h l l ba col add. a10 write/writeap illegal 4 l h l h ba col add. a10 read/readap illegal 4 l h h h x x no operation no operation 3 h x x x x x device deselect no operation or power down 3 row active l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge precharge 7 l l h h ba row add. bank activate illegal 4 l h l l ba col add. a10 write/writeap start write : optional ap(a10=h) 6 l h l h ba col add. a10 read/readap start read : optional ap(a10=h) 6 l h h h x x no operation no operation h x x x x x device deselect no operation read l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge termination burst: start the precharge l l h h ba row add. bank activate illegal 4 l h l l ba col add. a10 write/writeap termination burst: start write(optional ap) 8,9 l h l h ba col add. a10 read/readap termination burst: start read(optional ap) 8 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge termination burst: start the precharge 10 l l h h ba row add. bank activate illegal 4 l h l l ba col add. a10 write/writeap termination burst: start write(optional ap) 8 l h l h ba col add. a10 read/readap termination burst: start read(optional ap) 8,9 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 12 current state truth table (sheet 2 of 3) current state command action notes cs ras cas we ba0,ba1 a11-a0 description read with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 12 l h l h ba col add. a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 12 l h l h ba col add. a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst precharging l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge no operation: bank(s) idle after trp l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,12 l h h h x x no operation no operation: bank(s) idle after trp h x x x x x device deselect no operation: bank(s) idle after trp row activating l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,11,12 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,12 l h h h x x no operation no operation: row active after trcd h x x x x x device deselect no operation: row active after trcd
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 13 current state truth table (sheet 3 of 3) current state command action notes cs ras cas we ba0,ba1 a11-a0 description write recovering l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap start write: optional ap(a10=h) l h l h ba col add. a10 read/readap start read: optional ap(a10=h) 9 l h h h x x no operation no operation: row active after tdpl h x x x x x device deselect no operation: row active after tdpl write recovering with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,9,12 l h h h x x no operation no operation: precharge after tdpl h x x x x x device deselect no operation: precharge after tdpl refreshing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add. a10 write/writeap illegal 13 l h l h ba col add. a10 read/readap illegal 13 l h h h x x no operation no operation: idle after trc h x x x x x device deselect no operation: idle after trc mode register accessing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add. a10 write/writeap illegal 13 l h l h ba col add. a10 read/readap illegal 13 l h h h x x no operation no operation: idle after 2 clock cycles h x x x x x device deselect no operation: idle after 2 clock cycles
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 14 note : 1. h: logic high, l: logic low, x: don?t care, ba: bank address, ap: auto precharge. 2. all entries assume that cke was ac tive during the preceding clock cycle. 3. if both banks are idle and cke is inactive, then in power down cycle 4. illegal to bank in specified states. function may be legal in the bank indicated by bank address, depending on the state of that bank. 5. if both banks are idle and cke is inactive, then self refresh mode. 6. illegal if trcd is not satisfied. 7. illegal if tras is not satisfied. 8. must satisfy burs t interrupt condition. 9. must satisfy bus contentio n, bus turn around, and/or write recovery requirements. 10. must mask preceding data which don?t satisfy tdpl. 11. illegal if trrd is not satisfied 12. illegal for single bank, but legal for other banks in multi-bank devices. 13. illegal for all banks. 14. mode register set and extended mode register set is same command truth table except ba1.
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 15 cke enable(cke) truth table note : 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clo ck and other inputs are re-enabled asynchronously. when exiting power down mo de, a nop (or device deselect) command is required on the first positive edge of clock after cke goes high. 3. the address inputs depend on the command that is issued. 4. the precharge power down mode , the self refresh mode, and the mode register set can only be entered from the all banks idle state. 5. when cke has a low to high transition, the clock and other inputs are re-enabled asynchronously. when exiting deep power down mode, a nop (or device deselect) command is required on the first positive edge of clock after cke goes high and is maintained for a minimum 200 sec. current state cke command action notes previous cycle current cycle cs ras cas we ba0, ba1 a11- a0 self refresh h x x x x x x x invalid 1 l h h x x x x x exit self refresh with device deselect 2 l h l h h h x x exit self refresh with no oper- ation 2 l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 l l x x x x x x maintain self refresh power down h x x x x x x x invalid 1 l h h x x x x x power down mode exit, all banks idle 2 l h l x x x x x illegal 2 l l x x x x x x maintain power down mode deep power down h x x x x x x x invalid 1 l h x x x x x x deep power down mode exit 5 l l x x x x x x maintain deep power down mode all banks idle h h h x x x refer to the idle state section of the current state truth table 3 h h l h x x 3 h h l l h x 3 h h l l l h x x auto refresh h h l l l l op code mode register set 4 h l h x x x refer to the idle state section of the current state truth table 3 h l l h x x 3 h l l l h x 3 h l l l l h x x entry self refresh 4 h l l l l l op code mode register set l x x x x x x x power down 4 any state other than listed above h h x x x x x x refer to operations of the cur- rent state truth table h l x x x x x x begin clock suspend next cycle l h x x x x x x exit clock suspend next cycle l l x x x x x x maintain clock suspend
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 16 absolute maximum ratings parameter symbol rating unit ambient temperature t a tbd o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -1.0 ~ 3.6 v voltage on v dd relative to v ss v dd -1.0 ~ 3.6 v voltage on v ddq relative to v ss v ddq -1.0 ~ 3.6 v short circuit output current i os 50 ma power dissipation pd 1 w soldering temperature . time t solder 260 . 10 o c . sec note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (ta= -25 to 70 ) parameter symbol min typ max unit note power supply voltage v dd 2.3 2.5 2.7 v 1 power supply voltage v ddq 1.65 - 2.7 v 1, 2 input high voltage v ih 0.8*v ddq - v ddq+ 0.3 v 1, 2, 3 input low voltage v il -0.3 - 0.2*v ddq v 1, 2, 3 note : 1. all voltages are referenced to v ss = 0v 2. v ddq must not exceed the level of v dd 3. internal v ref = 0.9v ac operating test condition (ta= -25 to 70, v dd = 2.5v, v ss = 0v) ) parameter symbol value unit note ac input high/low level voltage vih / vil tbd v input timing measurement reference level voltage vtrip 0.9 v input rise/fall time tr / tf 1 ns output timing measurement reference level voltage voutref vddq/2 v output load capacitance for access time measurement cl tbd pf
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 17 capacitance (ta=2.5 c, f=1mhz, hy5xxxxxxf seires) dc characteristics i (ta= -25 to 70) note : 1. v in = 0 to 2.5v. all other pins are not tested under v in =0v. 2. d out is disabled. v out = 0 to 1.95v. 3. i out = - 0.1ma 4. i out = + 0.1ma parameter pin symbol -h -/p/s/b unit minmaxminmax input capacitance clk c i1 2.5 3.0 2.3 3.0 pf a0~a11, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm c i2 1.5 3.0 1.5 3.0 pf data input/output capacitance dq0 ~ dq15 c i/o 4.0 5.5 4.0 6.0 pf parameter symbol min max unit note input leakage current i li -1 1 a 1 output leakage current i lo -1 1 a 2 output high voltage v oh vddq - 0.2 - v 3 output low voltage v ol - 0.2 v 4
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 18 dc characteristics ii (ta= -25 to 70) note : 1. idd1 and idd4 depend on output loading and cycle rates. specified values ar e measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii. 3. see the tables of next page for more specific idd6 current values. - normal power : hy5w2a6cf / hy57w2a1620ct series - low power : hy5w2a6clf / hy57w2a1620clt series - super low power : hy5w2a6csf / hy57w2a1620cst series - standard part : hy5w26cf / hy5w281620hct series parameter symbol test condition speed unit note -h -p -s -b operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 75 65 60 60 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 0.5 ma i dd2ps cke v il (max), t ck = 0.5 ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 7 ma i dd2ns cke v ih (min), t ck = input signals are stable. 7 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 5 ma i dd3ps cke v il (max), t ck = 5 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 15 ma i dd3ns cke v ih (min), t ck = input signals are stable. 15 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active 100 80 70 70 ma 1 auto refresh current i dd5 t rrc t rrc (min), all banks active 165 155 125 125 ma 2 self refresh current i dd6 cke 0.2v ma 3 standby current in deep power down mode tbd tbd 60 a
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 19 dc characteristics iii - normal (i dd6 ) (v dd =2.5v, v ddq =1.8v & 2.5v, v ss =0v) dc characteristics iii - low power (i dd6 ) (v dd =2.5v, v ddq =1.8v & 2.5v, v ss =0v) dc characteristics ii i - super low power (i dd6 ) (v dd =2.5v, v ddq =1.8v & 2.5v, v ss =0v) dc characteristics iii - standard part (i dd6 ) (v dd =2.5v, v ddq =1.8v & 2.5v, v ss =0v) te m p . ( o c) memory array unit 4 banks 2 banks 1 bank 70 400 280 230 a -25~45 300 210 170 a te m p . ( o c) memory array unit 4 banks 2 banks 1 bank 70 330 230 190 a -25~45 250 180 150 a te m p . ( o c) memory array unit 4 banks 2 banks 1 bank 70 250 180 150 a -25~45 180 130 110 a te m p . ( o c) memory array unit 4 banks -25~70 < 450 a * hy5w2a6cf-f / hy57w2a1620ct-f series * hy5w2a6clf-f / hy57w2a1620clt-f series * hy5w2a6csf-f / hy57w2a1620cst-f series * hy5w26cf-f / hy57w281620ct-f series
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 20 ac characteristics i (ac operating conditions unless otherwise noted) note : 1. assume tr / tf (input rise and fall time) is 1ns. if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter. 2. access time to be measured with input si gnals of 1v/ns edge rate, from 0.8v to 0.2v. if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter. parameter symbol hp sb unit note min max min max min max min max system clock cycle time cas latency=3 tck3 7.5 1000 10 1000 10 1000 15 1000 ns cas latency=2 tck2 10 10 12 15 ns clock high pulse width tchw 2.5 - 3 - 3 - 3.5 - ns 1 clock low pulse width tclw 2.5 - 3 - 3 - 3.5 - ns 1 access time from clock cas latency=3 tac3 - 5.4 - 7 - 7 - 9 ns 2 cas latency=2 tac2 - 7 - 7 - 8 - 9 ns data-out hold time toh 2.7 - 3 - 3 - 3 - ns data-input setup time tds 1.5 - 2 - 2 - 2 - ns 1 data-input hold time tdh 0.8 - 1 - 1 - 1 - ns 1 address setup time tas 1.5 - 2 - 2 - 2 - ns 1 address hold time tah 0.8 - 1 - 1 - 1 - ns 1 cke setup time tcks 1.5 - 2 - 2 - 2 - ns 1 cke hold time tckh 0.8 - 1 - 1 - 1 - ns 1 command setup time tcs 1.5 - 2 - 2 - 2 - ns 1 command hold time tch 0.8 - 1 - 1 - 1 - ns 1 clk to data output in low-z time tolz 1 - 1 - 1 - 1 - ns clk to data output in high-z time cas latency=3 tohz3 2.7 5.4 3 6 3 6 3 9 ns cas latency=2 tohz2 2.7 7 3 6 3 6 3 9 ns
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 21 ac characteristics ii (ac operating conditions unless otherwise noted) note : 1. a new comman d can be given trrc afte r self refresh exit. parameter symbol hp sb unit note min max min max min max min max ras cycle time trc 65 - 70 - 70 - 90 - ns ras to cas delay trcd 20 - 20 - 30 - 30 - ns ras active time tras 45 100k 50 100k 50 100k 60 100k ns ras precharge time trp 20 - 20 - 30 - 30 - ns ras to ras bank active delay trrd 15 - 20 - 20 - 20 - ns cas to cas delay tccd 1 - 1 - 1 - 1 - tck write command to data-in delay twtl 0 - 0 - 0 - 0 - tck data-in to precharge command tdpl 2 - 1 - 1 - 1 - tck data-in to active command tdal 5 - 3 - 3 - 3 - tck dqm to data-out hi-z tdqz 2 - 2 - 2 - 2 - tck dqm to data-in mask tdqm 0 - 0 - 0 - 0 - tck mrs to new command tmrd 2 - 2 - 2 - 2 - tck precharge to data output high-z cas latency=3 tproz3 3 - 3 - 3 - 3 - tck cas latency=2 tproz2 2 2 2 2 tck power down exit time tdpe 1 - 1 - 1 - 1 - tck self refresh exit time tsre 1 - 1 - 1 - 1 - tck 1 refresh time tref - 64 - 64 - 64 - 64 ns
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 22 special operation for low power consumption deep power down mode deep power down mode is an operating mode to achieve maxi mum power reduction by cutting the power of the whole mem- ory array of the devices. data will not be retained once the de vice enters deep power down mode. full initialization is required when the device exits from deep power down mode. truth table deep power down mode entry the deep power down mode is entered by having /cs and /we held low with /ras and /cas high at the rising edge of the clock, while cke is low. the following diagr am illustrates deep power down mode entry. current state command cken-1 cken cs ras cas we idle deep power down entry h l l h h l deep power down deep power down exit l h x x x x clk cke cs ras cas we trp precharge if needed deep power down entry
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 23 deep power down mode (continued) deep power down mode exit sequence the deep power down mode is exited by asserting cke high. after the exit, the following sequence is needed to enter a new command. 1. maintain nop in put conditions for a minimum of 200 sec 2. issue precharge commands for all banks of the device 3. issue 8 or more auto refresh commands 4. issue a mode register set comma nd to initialize the mode register 5. issue an extended mode register set comm and to initialize the extended mode register the following timing diagram illustrates deep power down mode exit sequence. clk cke cs ras cas we deep power down exit all banks precharge auto refresh auto refresh mode register set extended mode register set new command accepted here 200 s trp trc
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 24 package information 54 ball 0.8mm pitch 8.3mm x 10.5mm fbga (hy5xxxxxxf series) 10.50 6.40 0.80 8.30 0.80 6.40 1.070 0.340 0.450
hy5w2a6c(l/s)f-f / hy57w2a1620hc(l/s)t -f hy5w26cf-f / hy57w281620hct-f rev. 1.3 / dec. 01 25 package information 400mil 54pin thin small outl ine package (hy5xxxxxxt series) unit : mm(inch)

▲Up To Search▲

Price & Availability of HY5W2A6CSF-HF

	To Download HY5W2A6CSF-HF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .